1. Field of the Invention
The present invention relates generally to semiconductor structures and manufacturing. More particularly the invention relates to the formation of multiple gate dielectric layer types for metal-oxide-semiconductor field effect transistors (MOSFETs).
2. Background
Advances in semiconductor manufacturing technology have led to the integration of millions of circuit elements, such as transistors, on a single integrated circuit (IC). In order to integrate increasing numbers of circuit elements onto an integrated it has been necessary to reduce the line widths of the various parts that make up an integrated circuit. Not only have interconnect line widths become smaller, but so have the dimensions of metal-oxide-semiconductor field effect transistors.
MOSFETs are also sometimes referred to as insulated gate field effect transistors (IGFETs). Most commonly, theses devices are referred to simply as FETs, and are so referred to in this disclosure.
Transistor scaling typically involves more than just the linear reduction of the FET width and length. For example, both source/drain (S/D) junction depth and gate dielectric thickness are also typically reduced in order to produce a FET with the desired electrical characteristics. Similarly, when in use, these reduced scale FETs are operated with scaled down voltages.
However, various circuit and system design constraints sometimes make it desirable to operate with more than one voltage supply. Unfortunately, transistors that have been scaled down into the deep sub-micron region are not generally capable of operating with higher voltages such as those found in older generation systems. In particular, the very thin gate dielectric layers that are required for deep sub-micron transistors are susceptible to damage from the very high electric fields impressed across them when the higher supply voltages are applied to the FET gate terminals.
What is needed is an integrated circuit having both high voltage and low voltage transistors integrated thereon. What is further needed are methods of making such an integrated circuit.
Briefly, an integrated circuit includes insulated gate field effect transistors having gate dielectric layers, wherein a nitrogen concentration in the gate dielectric varies between a first concentration at the gate electrode/gate dielectric interface and a second concentration at the gate dielectric/substrate interface.
In a further aspect of the present invention, an integrated circuit includes a plurality of insulated gate field effect transistors, wherein various ones of the plurality of transistors have different gate dielectric thicknesses and compositions.